CHAPTER I: Bolometric detectors
 

Figure 1.1: Spectral representation of investigated THz area [3]

Figure 1.2: a) Spectral density distribution of Planck’s blackbody radiation, b) example of thermal imaging in the far infrared [7]

Figure 1.3: Composite bolometric sensor with absorbing layer (η), bolometer resistive body thermally connected to the heat sink at constant temperature T₀.

Figure 1.4: R(T) characteristics of superconductor and semiconductor bolometers

Figure 1.5: a) Interaction mechanism in a metallic bolometer (normal bolometric effect) and b) in superconductor Hot Electron Bolometer (HEB)

Figure 1.6: Frequency characteristic of YBaCuO superconductor thin bolometer with normal bolometric area and with hot electron bolometric response, calculated upon a three thermal reservoir flux model [10]

Figure 1.7: a) NbN nanobolometer with log-periodic spiral antenna [14], b) detail of such a nanobolometer patterned in an ultra-thin superconductor Nb film [15]

Figure 1.8: Translation of frequency spectrum in heterodyne detection

Figure. 1.9: Heterodyne detection on a resistive bolometer body

CHAPTER II: MOS Transistor
 

Figure 2.1: a) Simple N-channel type transistor MOS with the substrate (bulk), drain, gate and source electrodes and thin insulating SiO₂ barrier b) schematic symbols of N and P-MOS transistors

Figure 2.1: a) Simple N-channel type transistor MOS with the substrate (bulk), drain, gate and source electrodes and thin insulating SiO₂ barrier b) schematic symbols of N and P-MOS transistors

Figure 2.2: Cross-section of planar N-MOS and P-MOS transistor in common P-type substrate, with indicated parasitic thyristor causing the latch-up effect

Figure  2.3: Cross-section e of a six-level metallic connection  [38]

Figure 2.4: Idealized MOS capacitor demonstrating the charge distribution dependence on the Gate-to-Bulk voltage V_GB. The gate is composed from the isolated elements of the voltage increasing along the channel (this is not real MOS device!)

Figure 2.5: N-Channel transistor MOS with induced channel, allowing the current transfer between the drain and source

Figure 2.6: N-Channel MOS transistor in saturation with a) V_DS=V_GS –V_TH: dashed line and b) V_DS > V_GS – V_TH : dark area

Figure 2.7: Measured characteristic of N-MOS transistor 15/5 µm  a) I_D  vs. V_GS with plotted g_m = dI_D/dV_GS  b) I_D vs. V_GS characteristic for the same transistor for various V_GS voltage

Figure 2.8: Effect of channel length modulation to the current I

Figure 2.9: Static small signal model of the MOS transistor containing the gate and substrate transconductance g_m an g_B, and channel resistance r_DS (=1/g_DS)

Figure 2.10: a) MOS terminal capacitances, b) physical interpretation off the MOS capacitances

Figure 2.10: b) physical interpretation off the MOS capacitances

Figure 2.11: C-V characteristic of the N-MOS 15 µm/5 µm transistor.(Terminals D, S, B are grounded)

Figure  2.12: C-V characteristic of gate capacitance plotted as function of V_GS and  V_DS showing the transition between the ohmic and saturation area (N-MOS 15µm/5µm)

Figure 2.13: AC small signal model of the MOS transistor

Figure 2.14: AC small signal model without substrate effect

Figure 2.15: I-V characteristic of transistor in linear, saturated and velocity saturated regions (plotted for N-MOS 10 µm/1 µm)

Figure 2.16: g_m/I_D characteristic of an N-MOS and P-MOS AMS 0.35µm transistor drawn from  Spice-level 7 model

Figure 2.17: Cross section of the AMS 0.35µm process

Figure  2.18: 45nm Intel TriGate transistor, a) AFM image; b) schematic design [34]

Figure  2.18: 45nm Intel TriGate transistor, a) AFM image; b) schematic design [34]

Figure 2.19: Single Electron Transistor (SET) a) structure with two tunnel junctions,
b) drain current periodicity with island charge [36]

Figure 2.19: Single Electron Transistor (SET), b) drain current periodicity with island charge [36]

CHAPTER III: Noise
 

Figure 3.1: Generated sequence of noise with Gaussian distribution

Figure 3.2: Demonstration of noise power transfer between two resistors maintained at different temperatures

Figure 3.3: Power spectral density (PSD) of generated white and 1/f noise sequences

Figure 3.4: Construction of an equivalent input noise voltage source

Figure 3.5: Equivalent input noise voltage of bipolar transistor as a function of input resistance R_S

Figure 3.6: Simplified small signal noise model of the MOS transistor

Figure 3.7: a) Feedback-free and b) feedback configuration of amplifiers with noise source modelling the noise of input amplifier stage

Figure 3.8: Chopper (auto zero) amplifier reducing the 1/f noise

Figure 3.9: Josephson junction composed of two superconducting electrodes and weak insulator link

Figure 3.11: a) DC SQUID realized with two Josephson junction, b) schematic design with an external coupling inductance